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19-4307; Rev 1; 12/08
Complete DDR2 and DDR3 Memory Power-Management Solution
General Description
The MAX17000A pulse-width modulation (PWM) controller provides a complete power solution for notebook DDR, DDR2, and DDR3 memory. It comprises a stepdown controller, a source-sink LDO regulator, and a reference buffer to generate the required VDDQ, VTT, and VTTR rails. The VDDQ rail is supplied by a step-down converter using Maxim's proprietary Quick-PWMTM controller. The high-efficiency, constant-on-time PWM controller handles wide input/output voltage ratios (low duty-cycle applications) with ease and provides 100ns response to load transients while maintaining a relatively constant switching frequency. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. The controller senses the current to achieve an accurate valley current-limit protection. It is also built in with overvoltage, undervoltage, and thermal protections. The MAX17000A can be set to run in three different modes: power-efficient SKIP mode, low-noise forced-PWM mode, and standby mode to support memory in notebook computer standby operation. The switching frequency is programmable from 200kHz to 600kHz to allow small components and high efficiency. The VDDQ output voltage can be set to a preset 1.8V or 1.5V, or be adjusted from 1.0V to 2.5V by an external resistor-divider. This output has 1% accuracy over line-and-load operating range. The MAX17000A includes a 2A source-sink LDO regulator for the memory termination VTT rail. This VTT regulator has a 5mV deadband that either sources or sinks, ideal for the fast-changing load burst present in memory termination applications. This feature also reduces output capacitance requirements. The VTTR reference buffer sources and sinks 3mA, providing the reference voltage needed by the memory controller and devices on the memory bus. The MAX17000A is available in a 24-pin, 4mm x 4mm, thin QFN package.
Features
o SMPS Regulator (VDDQ) Quick-PWM with 100ns Load-Step Response Output Voltages--Preset 1.8V, 1.5V, or Adjustable 1.0V to 2.5V 1% VOUT Accuracy Over Line and Load 26V Maximum Input Voltage Rating Accurate Valley Current-Limit Protection 200kHz to 600kHz Switching Frequency o Source/Sink Linear Regulator (VTT) 2A Peak Source/Sink Low-Output Capacitance Requirement Output Voltages-Preset VDDQ/2 or REFIN Adjustable from 0.5V to 1.5V o Soft-Start/Soft-Shutdown o SMPS Power-Good Window Comparator o VTT Power-Good Window Comparator o Selectable Overvoltage Protection o Undervoltage/Thermal Protections o 3mA Reference Buffer (VTTR)
MAX17000A
Ordering Information
PART TEMP RANGE PIN-PACKAGE MAX17000AETG+ -40C to +85C 24 Thin QFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration
TOP VIEW
DL 18 VDD 19 PGND1 20 AGND 21 SKIP 22 VCC 23 SHDN 24 1 OVP 2 PGOOD1 3 PGOOD2 4 STDBY 5 VTTS 6 VTTR
17
16
15
14
13 12 11 10 CSL FB REFIN VTTI VTT PGND2
MAX17000A
*EP
CSH 9 8 7
Applications
Notebook Computers DDR, DDR2, and DDR3 Memory Supplies SSTL Memory Supplies
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
*EXPOSED PAD
THIN QFN 4mm x 4mm
________________________________________________________________ Maxim Integrated Products
TON
BST
DH
LX
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
ABSOLUTE MAXIMUM RATINGS
TON to PGND1 .......................................................-0.3V to +28V VDD to PGND1..........................................................-0.3V to +6V VCC to VDD ............................................................-0.3V to +0.3V OVP to AGND ...........................................................-0.3V to +6V SHDN, STDBY, SKIP to AGND .................................-0.3V to +6V REFIN, FB, PGOOD1, PGOOD2 to AGND ................................-0.3V to (VCC + 0.3V) CSH, CSL to AGND ....................................-0.3V to (VCC + 0.3V) DL to PGND1..............................................-0.3V to (VDD + 0.3V) BST to PGND1...........................................................-1V to +34V BST to LX..................................................................-0.3V to +6V DH to LX ....................................................-0.3V to (VBST + 0.3V) BST to VDD .............................................................-0.3V to +26V VTTI to PGND2 .........................................................-0.3V to +6V VTT to PGND2 ............................................-0.3V to (VTTI + 0.3V) VTTS to AGND............................................-0.3V to (VCC + 0.3V) VTTR to AGND ..........................................-0.3V to (VCSL + 0.3V) PGND1, PGND2 to AGND.....................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 24-Pin, 4mm x 4mm Thin QFN (derated 27.8mW/C above +70C) ..........................2222mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER PWM CONTROLLER Input Voltage Range VIN VCC, VDD FB = AGND Output-Voltage Accuracy Output-Voltage Range Load Regulation Error Line Regulation Error Soft-Start Ramp Time Soft-Stop Ramp Time Soft-Stop Threshold RTON = 96.75k 167ns nominal On-Time Accuracy (Note 2) t ON VIN = 12V, VCSL = 1.2V (600kHz), -15 -10 -15 t SSTART t SSTOP VCSL VCSL VCSH - VCSL = 0 to 18mV, SKIP = VCC VDD = 4.5V to 5.5V, VIN = 4.5V to 26V Rising edge of SHDN Falling edge of SHDN VIN = 4.5V to 26V, SKIP = VCC FB = VCC FB = Adj 3 4.5 1.485 1.782 0.99 1 0.1 0.25 1.4 2.8 25 +15 +10 +15 % 2.1 1.500 1.800 1.000 26 5.5 1.515 1.818 1.01 2.7 V % % ms ms mV V V SYMBOL CONDITIONS MIN TYP MAX UNITS
RTON = 200k (300kHz), 333ns nominal RTON = 303.25k (200kHz), 500ns nominal
2
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Complete DDR2 and DDR3 Memory Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Minimum Off-Time Quiescent Supply Current (VDD) SYMBOL t OFF(MIN) IDD (Note 2) FB forced above 1.0V, STDBY = AGND or VCC, TA = +25C FB forced above 1.0V (PWM, VTT, and VTTR blocks); STDBY = VCC FB forced above 1.0V (PWM and VTTR blocks); STDBY = AGND SHDN = AGND, TA = +25C SHDN = AGND, VIN = 26V, VDD = 0 or 5V, TA = +25C 1.0 VTTI = 2.8V, REFIN = 1.4V, no load SHDN = AGND, TA = +25C VTTI = 2.8V, REFIN = 1.4V, TA = +25C VREFIN -50 0.5 VCC 0.3 High-side on-resistance (source, I VTT = 0.1A) Low-side on-resistance (sink, I VTT = 0.1A) VTT Output-Accuracy Source Load (VREFIN - 5mV) or (VCSL/2 - 5mV) to VTTS, VTT = VTTS VREFIN = 1V, I VTT = +50A VREFIN = 0.5V to 1.5V, I VTT = +300mA VREFIN = 1V, I VTT = -50A VREFIN = 0.5V to 1.5V, I VTT = -300mA +50A to +1A 2 -4 160 16 0.1 1.0 A -5 +5 13 1 4 -2 17 mV/A mV A s -5 -5 +5 mV 0.12 0.18 0.25 0.36 +5 mV 10 CONDITIONS MIN TYP 250 0.01 2 900 0.01 0.01 MAX 350 1.00 4 1500 5 1.00 UNITS ns A mA A A A
MAX17000A
Quiescent Supply Current (VCC)
ICC
Shutdown Supply Current (VDD + VCC) TON Shutdown Current LINEAR REGULATOR (VTT) VTTI Input Voltage Range VTTI Supply Current VTTI Shutdown Current REFIN Input Bias Current REFIN Range REFIN Disable Threshold
ICC + IDD ITON
VTTI IVTTI
2.8 50 10 +50 1.5
V A A nA V V
VTT Internal MOSFET
VTT Output-Accuracy Sink Load VTT Load Regulation VTT Line Regulation VTT Current Limit VTT Current-Limit Soft-Start Time VTT Discharge MOSFET VTTS Input Current
(VREFIN + 5mV) or (VCSL/2 + 5mV) to VTTS, VTT = VTTS -50A to -1A 1.0V Sink VTTI Source I VTT
2.8V, I VTT = 100mA
With respect to internal VTT_EN signal OVP = VCC TA = +25C
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3
Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER REFERENCE BUFFER (VTTR) VTTR Output Accuracy (Adj) VTTR Output Accuracy (Preset) VTTR Maximum Recommended Current FAULT DETECTION (SMPS) SMPS OVP and PGOOD1 Upper Trip Threshold SMPS OVP and PGOOD1 Upper Trip Threshold Fault-Propagation Delay SMPS Output Undervoltage Fault-Propagation Delay SMPS PGOOD1 Lower Trip Threshold PGOOD1 Lower Trip Threshold Propagation Delay PGOOD1 Output Low Voltage PGOOD1 Leakage Current TON POR Threshold FAULT DETECTION (VTT) PGOOD2 Upper Trip Threshold PGOOD2 Lower Trip Threshold PGOOD2 Propagation Delay PGOOD2 Fault Latch Delay PGOOD2 Output Low Voltage PGOOD2 Leakage Current FAULT DETECTION Thermal-Shutdown Threshold VCC Undervoltage Lockout Threshold CSL Discharge MOSFET T SHDN Hysteresis = 15C 3.8 160 4.1 16 4.4 C V Rising edge, IC disabled below this level VUVLO(VCC) hysteresis = 200mV OVP = VCC I PGOOD2 t PGOOD2 Hysteresis = 25mV Hysteresis = 25mV VTTS forced 50mV beyond PGOOD2 trip threshold VTTS forced 50mV beyond PGOOD2 trip threshold I SINK = 3mA VTTS = VREFIN (PGOOD2 high impedance), PGOOD2 forced to 5V, TA = +25C 8 -13 10 -10 10 5 0.4 1 13 -8 % % s ms V A I PGOOD1 VPOR(IN) t PGOOD1 t OVP FB forced 25mV above trip threshold 12 15 18 % REFIN to VTTR VCSL/2 to VTTR Source/sink I VTT = 1mA I VTT = 3mA I VTT = 1mA I VTT = 3mA -10 -20 -10 -20 5 +10 +20 +10 +20 mA mV SYMBOL CONDITIONS MIN TYP MAX UNITS
10
s
tUVP Measured at FB, hysteresis = 25mV FB forced 50mV below PGOOD1 trip threshold I SINK = 3mA FB = 1V (PGOOD1 high impedance), PGOOD1 forced to 5V, TA = +25C Rising edge, PWM disabled below this level; hysteresis = 200mV -12
200 -15 10 0.4 1 3.0 -18
s % s V A V
4
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Complete DDR2 and DDR3 Memory Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER CURRENT LIMIT Valley Current-Limit Threshold Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) SMPS GATE DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance DH Gate-Driver Source/ Sink Current DL Gate-Driver Source/ Sink Current Dead Time Internal BST Switch On-Resistance LX, BST Leakage Current INPUTS AND OUTPUTS Logic-Input Threshold Logic-Input Current Input Leakage Current Input Bias Current SHDN, STDBY, SKIP, OVP, rising edge hysteresis = 300mV/600mV (min/max) SHDN, STDBY, SKIP = 0 or VCC, TA = +25C CSH = 0 or VCC, TA = +25C CSL = 0 or VCC 1.30 -1 -1 55 1.65 2.00 +1 +1 100 V A A A RDH RDL IDH IDL(SRC) IDL(SNK) tDEAD RBST BST - LX forced to 5V DL high DL low DH forced to 2.5V, BST - LX forced to 5V DL forced to 2.5V DL forced to 2.5V DL rising, TA = +25C DL falling, TA = +25C IBST = 10mA, VDD = 5V internal design target VBST = VLX = 26V, SHDN = AGND, TA = +25C 10 15 1.5 1.5 0.6 1 1 3 25 35 4.5 0.001 20 A 5.0 5.0 3.0 A A ns VLIMIT VNEG VZX VCSH - VCSL VCSH - VCSL, SKIP = VCC VPGND1 - VLX 17 20 -23 1 25 mV mV mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17000A
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5
Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VCC = VDD = VSHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER PWM CONTROLLER Input Voltage Range VIN VCC, VDD FB = AGND Output-Voltage Accuracy VCSL VIN = 4.5V to 26V, SKIP = VCC FB = VCC FB = Adj RTON = 96.75k (600kHz), 167ns nominal On-Time Accuracy (Note 2) t ON VIN = 12V, VCSL = 1.2V RTON = 200k (300kHz), 333ns nominal RTON = 303.25k (200kHz), 500ns nominal Minimum Off-Time t OFF(MIN) (Note 2) FB forced above 1.0V (PWM, VTT, and VTTR blocks); STDBY = VCC FB forced above 1.0V (PWM and VTTR blocks); STDBY = AGND 1.0 VTTI = 2.8V, REFIN = 1.4V, no load 0.5 VCC 0.3 High-side on-resistance (source, IVTT = 0.1A) Low-side on-resistance (sink, I VTT = 0.1A) -50A to -1A I VTT +50A to +1A 0.25 0.36 17 mV/A 3 4.5 1.485 1.782 0.990 -15 26 5.5 1.520 1.820 1.020 +15 V V SYMBOL CONDITIONS MIN MAX UNITS
-10
+10
%
-15
+15 350 4 1500 ns mA A
Quiescent Supply Current (VCC)
ICC
LINEAR REGULATOR (VTT) VTTI Input Voltage Range VTTI Supply Current REFIN Range REFIN Disable Threshold VTT Internal MOSFET VTT Load Regulation VVTTI IVTTI VREFIN 2.8 50 1.5 V A V V
6
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Complete DDR2 and DDR3 Memory Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VCC = VDD = VSHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER REFERENCE BUFFER (VTTR) VTTR Output Accuracy (Adj) VTTR Output Accuracy (Preset) FAULT DETECTION (SMPS) PGOOD1 Output Low Voltage FAULT DETECTION (VTT) PGOOD2 Output Low Voltage FAULT DETECTION VCC Undervoltage-Lockout Threshold CURRENT LIMIT Valley Current-Limit Threshold SMPS GATE DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance Dead Time INPUTS AND OUTPUTS Logic-Input Threshold SHDN, STDBY, SKIP OVP, rising edge hysteresis = 300mV/600mV (min/max) 1.3 2 V RDH RDL tDEAD BST - LX forced to 5V DL high DL low DL rising DL falling 10 15 5 5 3 ns VLIMIT VCSH - VCSL 15 25 mV VUVLO(VCC) Rising edge, IC disabled below this level; hysteresis = 200mV 4.0 4.4 V I SINK = 3mA 0.4 V I SINK = 3mA 0.4 V REFIN to VTTR VCSL/2 to VTTR I VTT = 1mA I VTT = 3mA I VTT = 1mA I VTT = 3mA -10 -20 -10 -20 +10 +20 +10 +20 mV mV SYMBOL CONDITIONS MIN MAX UNITS
MAX17000A
Note 1: Limits are 100% production tested at TA = +25C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 2: On-time and off-time specifications are measured from 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times might differ due to MOSFET switching speeds.
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Typical Operating Characteristics
(MAX17000A Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
SMPS 1.5V EFFICIENCY vs. LOAD CURRENT
MAX17000A toc01
SMPS 1.5V EFFICIENCY vs. LOAD CURRENT
MAX17000A toc02
SMPS 1.5V EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 SKIP MODE STDBY = HIGH PWM MODE STDBY = HIGH OR LOW SKIP MODE STDBY = LOW
MAX17000A toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.01
SKIP MODE STDBY = LOW
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20
SKIP MODE STDBY = LOW
100
SKIP MODE STDBY = HIGH
PWM MODE STDBY = HIGH OR LOW
SKIP MODE STDBY = HIGH
PWM MODE STDBY = HIGH OR LOW
VIN = 7V 0.1 1 10
10 0.01 0.1 1 LOAD CURRENT (A)
VIN = 12V 10
10 0.01 0.1 1 LOAD CURRENT (A)
VIN = 20V 10
LOAD CURRENT (A)
SMPS 1.5V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17000A toc04
SMPS SWITCHING FREQUENCY vs. LOAD CURRENT
PWM MODE
MAX17000A toc05
SMPS VALLEY-CURRENT LIMIT vs. INPUT VOLTAGE
RSENSE = 2m 10.25 CURRENT LIMIT (A)
MAX17000A toc06
1.51
350 300 SWITCHING FREQUENCY (kHz) 250 200 150
10.50
OUTPUT VOLTAGE (V)
SKIP MODE
1.50 PWM MODE
10.00
SKIP MODE 100 50 VIN = 12V VOUT = 1.5V 0 2 4 6 8 10
9.75
1.49 0.001
VIN = 12V 0.01 0.1 1 10
0 LOAD CURRENT (A)
9.50 4 8 12 16 20 24 28 INPUT VOLTAGE (V)
LOAD CURRENT (A)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17000A toc07
PRESET 1.5V OUTPUT VOLTAGE DISTRIBUTION
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40 TA = +85C TA = +25C
MAX17000A toc08
100 NO LOAD PWM MODE, ICC + IDD SUPPLY CURRENT (mA) 10 PWM MODE, IIN STDBY = HIGH, SKIP MODE, ICC + IDD 1 STDBY = LOW, SKIP MODE, ICC + IDD 0.1 SKIP MODE, IIN 0.01 4 8 12 16 20 24
50
30
20
10
0 28 1.490 1.495 1.500 1.505 1.510 INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
8
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Complete DDR2 and DDR3 Memory Power-Management Solution
Typical Operating Characteristics (continued)
(MAX17000A Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
STARTUP WAVEFORM (HEAVY LOAD)
MAX17000A toc09
MAX17000A
SHUTDOWN WAVEFORM (DISCHARGE MODE ENABLED)
MAX17000A toc10
STANDBY TRANSITION WAVEFORM
MAX17000A toc11
DL SHDN VDDQ VTTR VTT PGOOD2 PGOOD1
STDBY VDDQ VTT TON DL LX
IVTT = 50mA
VDDQ VTT VTTR PGOOD1 ILX DL 200s/div SHDN: 5V/div PGOOD1: 2V/div RLOAD = 0.25 SKIP = GND VDDQ: 500mV/div ILX: 5A/div DL: 5V/div VTT: 500mV/div VTTR: 500mV/div
SHDN ILX ILX
400s/div DL: 5V/div VDDQ: 2V/div VTT: 1V/div VTTR: 1V/div PGOOD2: 5V/div PGOOD1: 5V/div SHDN: 10V/div ILX: 2A/div STDBY: 5V/div VDDQ: 1V/div VTT: 1V/div
100s/div TON: 1V/div DL: 5V/div LX: 10V/div ILX: 2A/div
STANDBY TRANSITION WAVEFORM
MAX17000A toc12
SMPS LOAD-TRANSIENT RESPONSE (PWM MODE)
MAX17000A toc13
SMPS LOAD-TRANSIENT RESPONSE (SKIP MODE)
MAX17000A toc14
STDBY VDDQ VTT TON DL LX
VDDQ
VDDQ
LX ILOAD
LX ILOAD
ILX ILX 10s/div STDBY: 5V/div VDDQ: 1V/div VTT: 1V/div TON: 1V/div DL: 5V/div LX: 10V/div ILX: 2A/div VDDQ: 50mV/div LX: 10V/div 20s/div ILOAD: 5A/div ILX: 5A/div VDDQ: 50mV/div LX: 10V/div ILX 20s/div ILOAD: 5A/div ILX: 5A/div
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9
Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Typical Operating Characteristics (continued)
(MAX17000A Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
VTT VOLTAGE vs. SOURCE/SINK LOAD CURRENT
MAX17000A toc16
OUTPUT OVERLOAD WAVEFORM
MAX17000A toc15
VTT OFFSET VOLTAGE DISTRIBUTION AT 300mA LOAD
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40 TA = +85C TA = +25C
MAX17000A toc17
0.79 0.78 0.77 VTT VOLTAGE (V) 0.76 0.75 0.74
50
DL VDDQ VTT VTTR PGOOD2 PGOOD1
30
20
ILX
10 0.73 VTTI = 1.5V 0.72 400s/div DL: 5V/div VDDQ: 1V/div VTT: 1V/div VTTR: 1V/div PGOOD2: 2V/div PGOOD1: 2V/div ILX: 10A/div -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 LOAD CURRENT (A) 0 -15.0 -12.5 -10.0 -7.5 -5.0 OFFSET VOLTAGE (mV)
VTT SOURCE CURRENT LIMIT
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40 TA = +85C TA = +25C
MAX17000A toc18
VTT SINK CURRENT LIMIT
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40 TA = +85C TA = +25C
MAX17000A toc19
VTT OVERLOAD FAULT WAVEFORMS (5ms TIMER)
MAX17000A toc20
50
50
DL ILX
30
30 VDDQ VTT VTTR 10 PGOOD1 PGOOD2
20
20
10
0 2.0 2.5 3.0 3.5 4.0 CURRENT LIMIT (A)
0 -4.0 -3.5 -3.0 -2.5 -2.0 DL: 5V/div ILX: 2A/div VDDQ: 2V/div VTT: 1V/div 1ms/div VTTR: 1V/div PGOOD1: 2V/div PGOOD2: 2V/div CURRENT LIMIT (A)
10
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Complete DDR2 and DDR3 Memory Power-Management Solution
Typical Operating Characteristics (continued)
(MAX17000A Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
VTT LOAD-TRANSIENT RESPONSE (SOURCE) IVTT BETWEEN 10mA AND 1.5A
MAX17000A toc21
MAX17000A
VTT LOAD-TRANSIENT RESPONSE (SINK)
MAX17000A toc22
IVTT IVTT
VTT_ac VTT_ac
VDDQ = 1.5V 20s/div IVTT: 1A/div VTT: 20mV/div
VDDQ = 1.5V 20s/div IVTT: 1A/div VTT: 20mV/div
VTT LOAD-TRANSIENT RESPONSE (SOURCE-SINK)
MAX17000A toc23
VTTR OUTPUT VOLTAGE vs. LOAD CURRENT
0.78
MAX17000A toc24
0.79
IVTT OUTPUT VOLTAGE (V) VDDQ = 1.5V 20s/div IVTT: 1A/div VTT: 50mV/div
0.77 0.76 0.75 0.74 0.73 0.72 0.71 0.70 -6 -4 -2 0 2 4 6 LOAD CURRENT (mA)
VTT_ac
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Pin Description
PIN NAME FUNCTION OVP Mode Control. This input selectively enables/disables the SMPS OV protection feature and output discharge mode. When enabled, the SMPS OV protection feature is enabled. Connect OVP to the following voltage levels for the desired function: High (> 2.4V) = Enable SMPS OV protection, and SMPS and VTT discharge FETs. Low (GND) = Disable SMPS OV protection, and SMPS and VTT discharge FETs. Open-Drain Power-Good Output. PGOOD1 is low when the SMPS output voltage is more than 15% (typ) beyond the normal regulation point, in standby, in shutdown, and during soft-start. After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the SMPS output is in regulation. Open-Drain Power-Good Output. PGOOD2 is low when the VTT output voltage is more than 10% (typ) beyond the normal regulation point, in standby, in shutdown, and during soft-start. After the SMPS soft-start circuit has terminated, PGOOD2 becomes high impedance if the VTT output is in regulation. Standby Control Input. When SHDN is high and STDBY is low, the MAX17000A turns off the VTT output (high-Z). When STDBY is high, normal SMPS operation resumes and the VTT output is enabled. Sense Pin for Termination Supply Output. Normally connected to the VTT pin to allow accurate regulation to VCSL/2 or the REFIN voltage. Termination Reference Buffer Output. VTTR tracks VCSL/2 when REFIN is connected to VCC. VTTR tracks VREFIN when a voltage between 0.5V to 1.5V is set at REFIN. Decouple VTTR to AGND with a 0.33F ceramic capacitor. Power Ground for VTT. Connect PGND2 externally to the underside of the exposed pad. Termination Power-Supply Output. Connect VTT to VTTS to regulate the VTT voltage to the VTTS regulation setting. Termination Power-Supply Input. VTTI is the input power supply to the VTT linear regulator. Normally connected to the output of the SMPS regulator for DDR applications. External Reference Input. REFIN sets the feedback regulation voltage (VTTR = VTTS = V REFIN) of the MAX17000A. Connect REFIN to VCC to use the internal VCSL/2 divider. Connect a 0.5V to 1.5V voltage input to set the adjustable output for VTT, VTTS, and VTTR. Feedback Input for SMPS Output. Connect to VCC for a fixed +1.8V output or to AGND for a fixed +1.5V output. For an adjustable output (1.0V to 2.7V), connect FB to a resistive divider from the output voltage. FB regulates to +1.0V. Negative Input of the PWM Output Current-Sense and Supply Input for VTTR. Connect CSL to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. CSL is also the path for the internal 16 discharge MOSFET when VCC UVLO occurs with OVP enabled. Positive Input of the PWM Output Current Sense. Connect CSH to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
1
OVP
2
PGOOD1
3
PGOOD2
4 5
STDBY VTTS
6 7 8 9
VTTR PGND2 VTT VTTI
10
REFIN
11
FB
12
CSL
13
CSH
12
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Complete DDR2 and DDR3 Memory Power-Management Solution
Pin Description (continued)
PIN NAME FUNCTION Switching Frequency Setting Input. An external resistor between the input power source and this pin sets the switching frequency per phase according to the following equation: 14 TON T SW = CTON x (RTON + 6.5k ) where CTON = 16.26pF. TON is high impedance in shutdown. 15 16 17 18 19 20 21 DH LX BST DL VDD PGND1 AGND High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO. Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1. Boost Flying Capacitor Connection. Connect to an external 0.1F, 6V capacitor as shown in Figure 1. The MAX17000A contains an internal boost switch. Synchronous-Rectifier Gate-Driver Output. DL swings from VDD to PGND1. Supply Voltage Input for the DL Gate Driver and 3.3V Reference/Analog Supply. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1F or greater ceramic capacitor. Power Ground. Ground connection for the low-side MOSFET gate driver. Analog Ground. Connect backside exposed pad to AGND. Pulse-Skipping Control Input. This input determines the mode of operation under normal steadystate conditions and dynamic output-voltage transitions: High (> 2.4V) = Forced-PWM operation Low (AGND) = Pulse-skipping mode Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass VCC to AGND with a 1F or greater ceramic capacitor. Shutdown Control Input. Connect to VCC for normal operation. When SHDN is pulled low, the MAX17000A slowly ramps down the output voltage to ground. When the internal target voltage reaches 25mV, the controller forces DL low, and enters the low current (1A) shutdown state. 24 SHDN When discharge mode is enabled by OVP (OVP = high), the CSL and VTT internal 16 discharge MOSFETs are enabled in shutdown. When discharge mode is disabled by OVP (OVP = low), LX, VTT, and VTTR are high impedance in shutdown. A rising edge on SHDN clears the fault OV protection latch. -- EP Exposed Pad. Connect backside exposed pad to AGND.
MAX17000A
22
SKIP
23
VCC
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Standard Application Circuits
The MAX17000A standard application circuit (Figure 1) generates the VDDQ, VTT, and VTTR rails for DDR, DDR2, or DDR3 in a notebook computer. See Table 1 for component selections. Table 2 lists the component manufacturers. Table 3 is the operating mode truth table.
Table 1. Component Selection for Standard Applications
COMPONENT Input Capacitor Output Capacitor Inductor Current-Sensing Resistor VOUT = 1.5V TO 1.8V AT 10A VIN = 7V TO 20V (300kHz) (2x) 10F, 25V Taiyo Yuden TMK432BJ106KM (2x) 330F, 2.5V ,12m (C2 case) SANYO 2R5TPE330MCC2 1.4H, 12A, 3.4m (typ) Sumida CDEP105(L)NP-1R4 2m, 0.5W (2010) Vishay WSL20102L000FEA 30V, 20A n-channel MOSFET (high side) Fairchild FDMS8690; 30V, 40A n-channel MOSFET (low side) Fairchild FDMS8660S VOUT = 1.5V TO 1.8V AT 6A VIN = 7V TO 16V (500kHz) 10F, 25V Taiyo Yuden TMK432BJ106KM (2x) 220F, 2.5V, 21m (B2 case) SANYO 2R5TPE220MLB 1.4H, 12A, 3.4m (typ) Sumida CDEP105(L)NP-1R4 3m, 0.5W (2010) Vishay WSL20103L000FEA 30V 20A n-channel MOSFET (high side) Fairchild FDMS8690; 30V 40A n-channel MOSFET (low side) Fairchild FDMS8660S
MOSFETs
Table 2. Component Suppliers
SUPPLIER INDUCTORS Dale (Vishay) NEC/TOKIN America, Inc. Panasonic Corp. Sumida Corp. TOKO America, Inc. CAPACITORS AVX Corp. KEMET Corp. Panasonic Corp. SANYO Electric Co., Ltd. Taiyo Yuden TDK Corp. SENSING RESISTORS Vishay MOSFET Fairchild Semiconductor DIODES Central Semiconductor Corp. Nihon Inter Electronics Corp. 631-435-1110 81-3-3343-84-3411 (Japan) www.centralsemi.com www.niec.co.jp 800-341-0392 (USA) www.fairchildsemi.com 402-563-6866 (USA) www.vishay,com 843-448-9411 (USA) 408-986-0424 (USA) 65-231-3226 (Singapore), 408-749-9714 (USA) 81-72-870-6310 (Japan), 619-661-6835 (USA) 03-3667-3408 (Japan), 408-573-4150 (USA) 847-803-6100 (USA), 81-3-5201-7241 (Japan) www.avxcorp.com www.kemet.com www.panasonic.com www.sanyodevice.com www.t-yuden.com www.component.tdk.com 402-563-6866 (USA) 510-324-4110 (USA) 65-231-3226 (Singapore), 408-749-9714 (USA) 408-982-9660 (USA) 858-675-8013 (USA) www.vishay,com www.nec-tokinamerica.com www.panasonic.com www.sumida.com www.tokoam.com PHONE WEBSITE
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Complete DDR2 and DDR3 Memory Power-Management Solution
Table 3. Operating Mode Truth Table
SHDN STDBY SKIP OPERATION SMPS output ramps up in skip mode with a 1.4ms (typ) ramp time. PGOOD1 is held low until the SMPS output is in regulation. VTT and VTTR ramp up to the final voltage based on VCSL/2 or VREFIN. PGOOD2 is held low until VTT is in regulation. SMPS output ramps up in skip mode with a 1.4ms ramp time. PGOOD1 is held low until the SMPS output is in regulation. VTT remains off throughout since STDBY is low. PGOOD2 stays low throughout. VTTR ramps up to the final voltage based on VCSL/2 or VREFIN. Standby mode is exited and the full current capability of the MAX17000A is available. VTT ramps up after the internal SMPS block is ready. VTT ramps to the final voltage based on VCSL/2 or VREFIN. PGOOD2 goes high when VTT is in regulation. SMPS is in forced-PWM mode. VTT and VTTR are enabled. PGOOD1 is high when the SMPS output is in regulation. PGOOD2 is high when VTT is in regulation. SMPS is in skip mode. VTT and VTTR are enabled. PGOOD1 is high when the SMPS output is in regulation. PGOOD2 is high when VTT is in regulation. SMPS is in forced-PWM mode. VTT is off and is in high impedance. PGOOD2 is forced low. VTTR is active and regulates to VCSL/2 or VREFIN. SMPS is in skip mode. VTT is off and is high impedance. PGOOD2 is forced low. VTTR is active and regulates to VCSL/2 or VREFIN. Skip mode is exited as the MAX17000A ramps the output down to zero. VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes low. Skip mode is exited as the MAX17000A ramps the output down to zero. VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes low. VTT is not enabled throughout soft-shutdown. DL low. Internal16 OVP is low. discharge MOSFETs on CSL and VTT enabled if OVP is high, but disabled if
MAX17000A
1
L
H
L
H
X
2
L
H
L
X
3
H
L
H
X
4
H
H
H
5
H
H
L
6
H
L
H
7
H
L
L
8
H
L
H
X
9
H
L
L
X
10
L
X
X
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
1 R3 100k R2 100k TON BST 2 3 19 CVDD 1F PGND 5V VCC CVCC 1F AGND SLP_S3# ON/OFF 4 24 22 STDBY SHDN SKIP PGND2 VCC 10 REFIN VTTI 9 7 CVTTI CVTT VTT VTTS VTTR EP 8 5 6 CVTTR 0.33F VTTR = VDDQ/2 VTT = VDDQ/2 +1V TO + 2.5V R1 10 23 VCC DH PGOOD1 PGOOD2 VDD LX DL PGND1 14 17 15 CBST 0.1F 16 18 20 CEQ NL REQ D1 CIN NH L1 RC VDDQ +1.8V OR 1.5V COUT RTON VIN 7V TO 20V RCS = RC RDCR REQ + RC
+5V
OVP
RDCR = L1 x ( 1 + 1 ) CEQ REQ RC
+5V
13 CSH 12 CSL
21
AGND
MAX17000A
FB 11
RFBA
RFBB
FB OPTIONS: 1. CONNECT FB TO 5V FOR FIXED +1.8V. 2. CONNECT FB TO GND FOR FIXED +1.5V. 3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE OUTPUT VOLTAGES.
Figure 1. MAX17000A Standard Application Circuit
Detailed Description
The MAX17000A complete DDR solution comprises a step-down controller, a source-sink LDO regulator, and a reference buffer. Maxim's proprietary Quick-PWM pulsewidth modulator in the MAX17000A is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. Figure 1 is the MAX17000A standard application circuit and Figure 2 is the MAX17000A functional diagram.
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The MAX17000A includes a 2A source-sink LDO regulator for the memory termination rail. The source-sink regulator features a dead band that either sources or sinks, ideal for the fast-changing short-period loads presenting in memory termination applications. This feature also reduces the VTT output capacitance requirement down to 1F, though load-transient response can still require higher capacitance values between 10F and 20F. The reference buffer sources and sinks 3mA, generating a reference rail for use in the memory controller and memory devices.
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
TON CSL ON-TIME COMPUTE TON TRIG ONE-SHOT DH LX VDD DL S R Q PGND1 Q tOFF(MIN) Q TRIG ONE-SHOT BST
S ERROR AMP R
Q
SMPS FAULT DETECTION OVF OVP VTT FAULT
1.2V SMPS FAULT INT_FB SMPS FAULT LATCH 0.7V 10ms TIMER SMPS RUN EA ZERO CROSSING
SKIP
1mV CSL
VALLEY CURRENT LIMIT
UVF
20mV
CSH
RUN
SOFT-START/ SOFT-STOP 1V REF INT_FB FB DECODE
SHDN
FB VCC
PGOOD1
POWER-GOOD1 OVF 1.15V VTTR WINDOW COMPARATOR VTTR
INT_REF
VTT FAULT
MAX17000A
POWER-GOOD2 1.4ms VTT WINDOW COMPARATOR VTTI VTT SMPS FAULT STDBY VDD - 0.3V REFIN VTT_EN R CSL R RUN OVP VCC UVLO PGND2 PGND1 VTT CSL 16 16 5mV PGND2 CSL 5ms TIMER VTT FAULT VTT SS CURRENT LIMIT 5mV VTT PGND2 VTT NEG CURRENT LIMIT VTT_EN VTT POS CURRENT LIMIT VDD
AGND
PGOOD2
VTTS VTTI
VTT VDD
PGND2
VTTR
Figure 2. MAX17000A Functional Diagram
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Complete DDR2 and DDR3 Memory Power-Management Solution
+5V Bias Supply (VDD, VCC) The MAX17000A requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's 95% efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator such as the MAX1615. The 5V bias supply powers both the PWM controller and internal gate-drive power, so the maximum current drawn is: IBIAS = IQ + fSWQG(MOSFETs) = 2mA to 20mA (typ)
where IQ is the current for the PWM control circuit, fSW is the switching frequency, and QG(MOSFETs) is the total gate-charge specification limits at VGS = 5V for the internal MOSFETs.
MAX17000A
tON =
CTON x (RTON + 6.5k) x (VCSL + 0.075V) VIN fSW = 1 CTON x (RTON + 6.5k)
where CTON = 16.26pF, and 0.075V is an approximation to accommodate for the expected drop across the low-side MOSFET switch. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: fSW = VOUT + VDIS tON x (VIN - VCHG + VDIS )
Free-Running Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator with voltage feed-forward. This architecture utilizes the output filter capacitor's ESR to act as a current-sense resistor, so the output ripple voltage can provide the PWM ramp signal. In addition to the general QuickPWM, the MAX17000A also senses the inductor current through DCR method or with a sensing resistor. Therefore, it is less dependent on the output capacitor ESR for stability. The control algorithm is simple: the high-side switch on-time is determined solely by a oneshot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (250ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time oneshot has timed out.
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the charging path, including the high-side switch, inductor, and PCB resistances; and t ON is the on-time calculated by the MAX17000A.
Automatic Pulse-Skipping Mode (SKIP = AGND)
In skip mode (SKIP = AGND), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. DC output-accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX17000A regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP = AGND and IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. However, the internal integrator corrects for most of it, resulting in very little load regulation. The MAX17000A always uses skip mode during startup, regardless of the SKIP and STDBY setting. The SKIP and STDBY controls take effect after soft-start is done. See Figure 3.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltages. The high-side switch on-time is inversely proportional to the battery voltage as measured by the VIN input, and proportional to the output voltage. An external resistor between the input power source and TON pin sets the switching frequency per phase according to the following equation:
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Complete DDR2 and DDR3 Memory Power-Management Solution
reverses at light loads while DH maintains a duty factor of VOUT/VIN. The benefit of forced-PWM mode is to keep a fairly constant switching frequency. However, forcedPWM operation comes at a cost: the no-load 5V bias current remains between 2mA to 20mA, depending on the switching frequency. STDBY = AGND overrides the SKIP pin setting, forcing the MAX17000A into standby. The MAX17000A switches to forced-PWM mode during shutdown, regardless of the state of SKIP and STDBY levels.
MAX17000A
I = t INDUCTOR CURRENT
VIN - VOUT L IPEAK
ILOAD = IPEAK/2
Standby Mode (STDBY)
0 ON-TIME TIME
It should be noted that standby mode in the MAX17000A corresponds to computer system standby operation, and is not referring to the MAX17000A shutdown status. When standby mode is enabled (STDBY = AGND), VTT is disabled (high impedance) but VTTR remains active. When standby mode is disabled (STDBY = VCC), the VTT block is enabled and the VTT output capacitor is charged. The VTT soft-start current limit increases linearly from zero to its maximum current limit in 160s (typ), keeping the input VTTI inrush low. See Figure 4.
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
Forced-PWM Mode (SKIP = VCC) The low-noise forced-PWM mode (SKIP = VCC) disables the zero-crossing comparator, which controls the lowside switch on-time. This forces the low-side gate-drive waveform to constantly be the complement of the highside gate-drive waveform, so the inductor current
STDBY SMPS OUTPUT VTTR OUTPUT
VTT OUTPUT VTT CURRENT LIMIT
VTT HIGH-IMPEDANCE
160s PGOOD1 PGOOD2 STANDBY TIMING
Figure 4. MAX17000A Standby Mode Timing
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Valley Current-Limit Protection
The MAX17000A uses the same valley current-limit protection employed on all Maxim Quick-PWM controllers. If the current exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and battery voltage. When combined with the undervoltage-protection circuit, this current-limit method is effective in almost every circumstance. In forced-PWM mode, the MAX17000A also implements a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 115% of the positive current limit. See Figure 5. PGOOD2 is the open-drain output for a window comparator that continuously monitors the VTT output. PGOOD2 is actively held low in standby, shutdown, and during soft-start. PGOOD2 becomes high impedance as long as the VTT output voltage is within 10% of the regulation voltage. When the VTT output exceeds the 10% threshold, the MAX17000A pulls PGOOD2 low. If PGOOD2 remains low for 5ms (typ), the MAX17000A latches off with the soft-shutdown sequence. For logic-level output voltages, connect an external 100k pullup resistor from PGOOD1 and PGOOD2 to VDD.
POR, UVLO
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start circuit and preparing the controller for power-up. When OVP protection is enabled, a rising edge on POR turns on the 16 discharge MOSFET on CSL and VTT. When OVP is disabled, the internal 16 discharge MOSFETs on CSL and VTT also remain off. V CC undervoltage lockout (UVLO) circuitry inhibits switching until VCC reaches 4.1V (typ). When VCC rises above 4.1V, the controller activates the PWM controller and initializes soft-start. When VCC drops below the UVLO threshold (falling edge), the controller stops, DL is pulled low, and the internal 16 discharge MOSFETs on the CSL and VTT outputs are enabled, if OVP is enabled.
IPEAK
ILOAD INDUCTOR CURRENT
ILIMIT ILIM(VAL) = ILOAD(MAX) 1-
( LIR ) 2
Soft-Start and Soft-Shutdown
Soft-start and soft-shutdown for the MAX17000A PWM block is voltage based. Soft-start begins when SHDN is driven high. During soft-start, the PWM output is ramped up from 0V to the final set voltage in 1.4ms. This reduces inrush current and provides a predictable ramp-up time for power sequencing. The MAX17000A always uses skip mode during startup, regardless of the SKIP and STDBY setting. The SKIP and STDBY controls take effect after soft-start is done. The MAX17000A VTT LDO regulator uses a current-limited soft-start function. When the VTT block is enabled, the internal source and sink current limits are linearly increased from zero to the full-scale limit in 160s. Fullscale current limit is available when the VTT output is in regulation, or after 160s, whichever is earlier. The VTTR reference buffer does not have any soft-start control.
0
TIME
Figure 5. Valley Current-Limit Threshold Point
Power-Good Outputs (PGOOD1 and PGOOD2)
The MAX17000A features two power-good outputs. PGOOD1 is the open-drain output for a window comparator that continuously monitors the SMPS output. PGOOD1 is actively held low in shutdown and during soft-start and soft-shutdown. After the soft-start terminates, PGOOD1 becomes high impedance as long as the SMPS output voltage is between 115% (typ) and 85% (typ) of the regulation voltage. When the SMPS output voltage exceeds the 115%/85% regulation window, the MAX17000A pulls PGOOD1 low. Any fault condition on the SMPS output forces PGOOD1 and PGOOD2 low and latches off until the fault latch is cleared by toggling SHDN or cycling VCC power below 1V. Detection of an OVP event immediately pulls PGOOD1 low, regardless of the OVP state (OVP enabled or disabled).
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
SHDN STDBY
INT_REF
REFOK SMPS_RUNOK 1.4ms 2.8ms
SMPS OUTPUT
25mV
VTT OUTPUT VTTR OUTPUT VTT CURRENT LIMIT 160s
PGOOD1 PGOOD2
DL VTT 16 FET CSL 16 FET
SKIP
FPWM
Figure 6. MAX17000A Startup/Shutdown Timing with OVP Enabled
Soft-shutdown begins after SHDN goes low, an output undervoltage fault occurs, or a thermal fault occurs. A fault on the SMPS (UV fault for more than 200s (typ)), or fault on the VTT output that persists for more than 5ms (typ), triggers shutdown of the whole IC. During soft-shutdown, the output is ramped down to 0V in 2.8ms, reducing negative inductor currents that can cause negative voltages on the output. At the end of soft-shutdown, DL is driven low.
When OVP is enabled (OVP = VCC), the internal 16 discharging MOSFETs on CSL and VTT are enabled until startup is triggered again by a rising edge of SHDN. When OVP is disabled (OVP = AGND), the CSL and VTT internal 16 discharging MOSFETs are not enabled in shutdown.
Output Fault Protection
The MAX17000A provides overvoltage/undervoltage fault protections for the PWM output. Drive OVP to enable and disable fault protection as shown in Table 4.
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Table 4. Fault Protection and Shutdown Setting Truth Table
OVP MODE Shutdown (SHDN = low) REACTION/DRIVER STATE DL immediately pulled low. VTTR tracks the SMPS output during soft-shutdown. CSL and VTT are high impedance at the end of soft-shutdown (16 discharge MOSFETs disabled). DL immediately pulled low. VTTR tracks the SMPS output during soft-shutdown. CSL and VTT are high impedance at the end of soft-shutdown (16 discharge MOSFETs disabled). Controller remains active (normal operation). Note: An OVP detection still pulls PGOOD1 low. COMMENT Outputs highimpedance in shutdown.
SMPS UVP OVP Disabled Discharge Disabled (OVP = Low)
SMPS latched fault condition. Only PGOOD1 pulled low; fault not latched. VTT latched fault condition if fault persists for more than 5ms (typ).
SMPS OVP (disabled)
PGOOD2 immediately pulled low. VTT < -90% or Soft-shutdown initiated if fault persists for more than 5ms (typ). DH VTT > +110% not used in soft-shutdown. DL low after soft-shutdown completed. VTTR tracks the SMPS output soft-shutdown. VCC UVLO falling edge DL and DH immediately pulled low. PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR blocks immediately disabled (high impedance, no 16 discharge on outputs). Soft-shutdown initiated. DL high after soft-shutdown completed. VTTR tracks the SMPS output during soft-shutdown. Internal 16 discharge MOSFETs on CSL and VTT enabled after soft-shutdown. Soft-shutdown initiated. DH not used in soft-shutdown. DL low after soft-shutdown completed. VTTR tracks the SMPS output during soft-shutdown. Internal 16 discharge MOSFETs on CSL and VTT enabled after soft-shutdown. DL immediately latched high, DH forced low. PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR blocks immediately shut down. Internal 16 discharge MOSFETs on CSL and VTT enabled. PGOOD2 immediately pulled low. Soft-shutdown initiated if fault persists for more than 5ms (typ). DH not used in soft-shutdown. DL low after soft-shutdown completed. VTTR tracks the SMPS output during soft-shutdown. Internal 16 discharge MOSFETs on CSL and VTT enabled after soft-shutdown. DL and DH immediately pulled low. PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR blocks immediately disabled. Internal 16 discharge MOSFETs on CSL and VTT enabled immediately.
--
Shutdown (SHDN = low)
16 discharge MOSFETs on CSL and VTT enabled in shutdown. SMPS latched fault condition.
SMPS UVP OVP Enabled Discharge Enabled (OVP = High)
SMPS OVP (enabled)
SMPS latched fault condition.
VTT < 90% or VTT > 110%
VTT latched fault condition if fault persists for more than 5ms (typ).
OVP Enabled Discharge Enabled (OVP = High)
VCC UVLO falling edge
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Complete DDR2 and DDR3 Memory Power-Management Solution
Table 4. Fault Protection and Shutdown Setting Truth Table (continued)
OVP MODE REACTION/DRIVER STATE DL and DH immediately pulled low. PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR blocks immediately disabled (high impedance, no 16 discharge on outputs). Activate INT_REF once VCC rises above UVLO, and SHDN = high. Once REFOK is valid (high), initiate the soft-start sequence. DL remains low until switching/soft-start begins. DL forced low. DL = Don't care. VCC less than 2VT is not sufficient to turn on the MOSFETs. COMMENT
MAX17000A
Thermal fault
Active-fault condition.
General Shutdown and Fault Conditions
VCC UVLO rising edge VCC POR rising edge VCC POR falling edge
--
-- --
SMPS Overvoltage Protection (OVP) If the output voltage of the SMPS rises 115% above its nominal regulation voltage while OVP is enabled (OVP = VCC), the controller sets its overvoltage fault latch, pulls PGOOD1 and PGOOD2 low, and forces DL high. The VTT and VTTR block shut down immediately, and the internal 16 discharge MOSFETs on CSL and VTT are turned on. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the battery fuse blows. Cycle VCC below 1V or toggle SHDN to clear the overvoltage fault latch and restart the controller. OVP is disabled when OVP is connected to AGND (Table 4). PGOOD1 upper threshold remains active at 115% of nominal regulation voltage even when OVP is disabled and the 16 discharge MOSFETs on CSL and VTT are not enabled in shutdown. SMPS Undervoltage Protection (UVP) If the output voltage of the SMPS falls below 85% of its regulation voltage for more than 200s (typ), the controller sets its undervoltage fault latch, pulls PGOOD1 and PGOOD2 low, and begins soft-shutdown pulsing DL. DH remains off during the soft-shutdown sequence initiated by an undervoltage fault. After soft-shutdown has completed, the MAX17000A forces DL and DH low, and enables the internal 16 discharge MOSFETs on CSL and VTT. Cycle VCC below 1V or toggle SHDN to clear the undervoltage fault latch and restart the controller. VTT Overvoltage and Undervoltage Protection If the output voltage of the VTT regulator exceeds 10% of its regulation voltage for more than 5ms (typ), the controller sets its fault latch, pulls PGOOD1 and PGOOD2 low, and begins soft-shutdown pulsing DL. DH remains off during the soft-shutdown sequence initiated by an undervoltage fault. After soft-shutdown has
completed, the MAX17000A forces DL and DH low, and enables the internal 16 discharge MOSFETs on CSL and VTT. Cycle VCC below 1V or toggle SHDN to clear the undervoltage fault latch and restart the controller.
Thermal-Fault Protection The MAX17000A features a thermal-fault protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls PGOOD1 and PGOOD2 low, and shuts down using the shutdown sequence. Toggle SHDN or cycle VCC power below VCC POR to reactivate the controller after the junction temperature cools by 15C.
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case input supply voltage allowed by the notebook's AC adapter voltage. The minimum value (V IN(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Most notebook loads generally exhibit ILOAD = ILOAD(MAX) x 80%. * Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) x 1 + 2
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: LIR ILIMIT(LOW) > ILOAD(MAX) x 1 2 where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the output sense element (inductor DCR or sense resistor). The valley current limit is fixed at 17mV (min) across the CSH to CSL differential input. Special attention must be made to the tolerance and thermal variation of the on-resistance in the case of DCR sensing. Use the worst-case maximum value for RDCR from the inductor data sheet, and add some margin for the rise in RDCR with temperature. A good general rule is to allow 0.5% additional resistance for each degree Celsius of temperature rise, which must be included in the design margin unless the design includes an NTC thermistor in the DCR network to thermally compensate the current-limit threshold. The current-sense method (Figure 7) and magnitude determine the achievable current-limit accuracy and power loss. The sense resistor can be determined by: RSENSE = VLIMIT/ILIMIT
*
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VOUT VIN - VOUT L= x fSW x ILOAD(MAX) x LIR VIN Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered
INPUT (VIN) DH LX NH CIN L SENSE RESISTOR LESL RSENSE CEQREQ = NL DL REQ CEQ COUT LESL RSENSE
MAX17000A DL
PGND1 CSH CSL
A) OUTPUT SERIES RESISTOR SENSING
Figure 7a. Current-Sense Configurations (Sheet 1 of 2)
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INPUT (VIN) DH LX NH CIN L INDUCTOR RDCR RCS = NL DL R1 R2 CEQ COUT RDCR = L CEQ 11 [ R1 + R2 ] R2 RDCR R1 + R2
MAX17000A DL
PGND1 CSH CSL
B) LOSSLESS INDUCTOR SENSING
FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 7b. Current-Sense Configurations (Sheet 2 of 2)
For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 7a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. However, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. This parasitic inductance (LESL) can be cancelled by adding an RC circuit across the sense resistor with an equivalent time constant: CEQ x REQ = LESL RSENSE
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential exists. The high-side gate driver (DH) sources and sinks 1.2A, and the low-side gate driver (DL) sources 1.0A and sinks 2.4A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET driver is powered by an internal boost switch charge pump at BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD).
PWM Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In core and chipset converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: V (RESR + RPCB ) I STEP LOAD(MAX) In low-power applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR.
Alternatively, low-cost applications that do not require highly accurate current-limit protection could reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 7b) with an equivalent time constant: RCS = and: RDCR = L 1 1 x + CEQ R1 R2 R2 x RDCR R1 + R2
where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
The maximum ESR to meet ripple requirements is: VIN x fSW x L RESR x VRIPPLE ( VIN - VOUT ) x VOUT where fSW is the switching frequency. With most chemistries (polymer, tantalum, aluminum, electrolytic), the actual capacitance value required relates to the physical size needed to achieve low ESR and the chemistry limits of the selected capacitor technology. Ceramic capacitors provide low ESR, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. Thus, the output capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. ESR vs. voltage rating) and cost. ceramic output capacitors can be compensated using either a DC-compensation or AC-compensation method. The DC-coupling requires fewer external compensation capacitors, but this also creates an output load line that depends on the inductor's DCR (parasitic resistance). Alternatively, the current-sense information can be AC-coupled, allowing stability to be dependent only on the inductance value and compensation components and eliminating the DC load line. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can allow significant output overshoot when stepping from full-load to no-load conditions, unless a small inductor value and high switching frequency are used to minimize the energy transferred from inductor to capacitor during load-step recovery. Unstable operation manifests itself in two related, but distinctly different ways: double pulsing and feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response undervoltage/overshoot.
PWM Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the in-phase feedback ripple relative to the switching frequency, which is typically dominated by the output ESR. The boundary of instability is given by the following equation: fSW 1 2 x REFF x COUT REFF = RESR + ACS x RSENSE where COUT is the total output capacitance, RESR is the total equivalent series resistance of the output capacitors, RSENSE is the effective current-sense resistance (see Figure 7), and ACS is the current-sense gain of 2. For a standard 300kHz application, the effective zero frequency must be well below 95kHz, preferably below 50kHz. With these frequency requirements, standard tantalum and polymer capacitors already commonly used have typical ESR zero frequencies below 50kHz, allowing the stability requirements to be achieved without any additional current-sense compensation. In the standard application circuit (Figure 1), the ESR needed to support a 15mV P-P ripple is 15mV/(10A x 0.3) = 5m. Two 330F, 9m polymer capacitors in parallel provide 4.5m (max) ESR and 1/(2 x 330F x 9m) = 53kHz ESR zero frequency. Ceramic capacitors have a high-ESR zero frequency, but applications with sufficient current-sense compensation can still take advantage of the small size, low ESR, and high reliability of the ceramic chemistry. By the inductor current DCR sensing, applications with
26
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation: I IRMS = LOAD VOUT x ( VIN - VOUT ) VIN The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to: IRMS = 0.5 x ILOAD
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Complete DDR2 and DDR3 Memory Power-Management Solution
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity. can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: QG(SW) PD (NH Switching) = VIN(MAX) x ILOAD x fSW IGATE C x VIN2 x fSW + OSS 2 where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
V 2 PD (NL Resistive) = 1- OUT x (ILOAD ) x RDS(ON) VIN(MAX)
MAX17000A
MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V IN(MIN) and V IN(MAX) . Calculate both these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Drivers (DH, DL) section).
MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:
V 2 PD (NH Resistive) = OUT x (ILOAD ) x RDS(ON) VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET
The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be "over designed" to tolerate: I ILOAD = IVALLEY(MAX) + INDUCTOR 2 ILOAD(MAX) x LIR = IVALLEY(MAX) + 2
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical.
VTTI Input Capacitor Stability Considerations
The value of the VTTI bypass capacitor is chosen to limit the amount of ripple/noise at VTTI, and the amount of voltage dip during a load transient. Typically, VTTI is connected to the output of the buck regulator, which already has a large bulk capacitor. Nevertheless, a ceramic capacitor of equivalent value to the VTT output capacitor must be used and must be added and placed as close as possible to the VTTI pin. This value must be increased with larger load current, or if the trace from the VTTI pin to the power source is long and has significant impedance.
Setting the PWM Output Voltage
Preset Output Voltages The MAX17000A's Dual ModeTM operation allows the selection of common voltages without requiring external components. Connect FB to AGND for a fixed 1.5V output, to V CC for a fixed 1.8V output, or connect FB directly to OUT for a fixed 1.0V output. Adjustable Output Voltage The output voltage can be adjusted from 1.0V to 2.7V using a resistive voltage-divider (Figure 8). The MAX17000A regulates FB to a fixed reference voltage (1.0V). The adjusted output voltage is:
R VOUT = VFB x 1 + FBA RFBB where VFB is 1.0V.
Setting VTT Output Voltage
The VTT output stage is powered from the VTTI input. The output voltage is set by the REFIN input. REFIN sets the feedback regulation voltage (VTTR = VTTS = VREFIN) of the MAX17000A. Connect a 0.1V to 2.0V voltage input to set the adjustable output for VTT, VTTS, and VTTR. If REFIN is tied to VCC, the internal CSL/2 divider is used to set VTT voltage; hence, VTT tracks the VCSL voltage and is set to VCSL/2. This feature makes the MAX17000A ideal for memory applications in which the termination supply must track the supply voltage.
VTT Output Capacitor Selection
A minimum value of 9F is needed to stabilize a 300mA VTT output. This value of capacitance limits the regulator's unity-gain bandwidth frequency to approximately 1.2MHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within the regulator's bandwidth, it is important that ceramic capacitors with low ESR and ESL be used.
L1 VOUT COUT
LX DL PGND1 NL D1
MAX17000A
CSH CSL RFBA FB RFBB
Figure 8. Setting VOUT with a Resistive Voltage-Divider Dual Mode is a trademark of Maxim Integrated Products, Inc.
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Since the gain bandwidth is also determined by the transconductance of the output FETs, which increases with load current, the output capacitor might need to be greater than 20F if the load current exceeds 1.5A, but can be smaller than 20F if the maximum load current is less than 1.5A. As a guideline, choose the minimum capacitance and maximum ESR for the output capacitor using the following: COUT _ MIN = 20F x ILOAD 1.5A
MAX17000A
PD(Total) = 2 W The 2W total power dissipation is within the 24-pin TQFN multilayer board power dissipation specification of 2.22W. The typical application does not source or sink continuous high currents. VTT current is typically 100mA to 200mA in the steady state. VTTR is down in the microamp range, though the Intel specification requires 3mA for DDR1 and 1mA for DDR2. True worstcase power dissipation occurs on an output short-circuit condition with worst-case current limit. The MAX17000A does not employ any foldback current limiting, and relies on the internal thermal shutdown for protection. Both the VTT and VTTR output stages are powered from the same VTTI input. Their output voltages are referenced to the same REFIN input. The value of the VTTI bypass capacitor is chosen to limit the amount of ripple/noise at VTTI, or the amount of voltage dip during a load transient. Typically, VTTI is connected to the output of the buck regulator, which already has a large bulk capacitor.
COUT_MIN needs to be increased by a factor of 2 for low-dropout operation: RESR _ MAX = 5m x ILOAD 1.5A
RESR_MAX value is measured at the unity-gain-bandwidth frequency given by approximately: fGBW = I 36 x LOAD COUT 1.5A
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = QGATE 200mV
Once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or voltage ripple at the output.
VTTR Output Capacitor Selection
The VTTR buffer is a scaled-down version of the VTT regulator, with much smaller output transconductance. Its compensation capacitor can, therefore, be smaller and its ESR larger than what is required for its larger counterpart. For typical applications requiring load current up to 4mA, a ceramic capacitor with a minimum value of 0.33F is recommended (R ESR < 0.3). Connect this capacitor between VTTR and the analog ground plane.
Power Dissipation
Power loss in the MAX17000A is the sum of the losses of the PWM block, the VTT LDO block, and the VTTR reference buffer: PD(PWM) = IBIAS x 5V = 40mA x 5V = 0.2 W PD(VTT) = 2 A x 0.9V = 1.8 W PD(VTTR) = 3mA x 0.9V = 2.7mW
where QGATE is the total gate charge specified in the high-side MOSFET's data sheet. For example, assume the FDS6612A n-channel MOSFET is used on the high side. According to the manufacturer's data sheet, a single FDS6612A has a maximum gate charge of 13nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 13nC = 0.065F 200mV
Selecting the closest standard value, this example requires a 0.1F ceramic capacitor.
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the topside of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. Minimize current-sensing errors by connecting CSH and CSL directly across the current-sense resistor (RSENSE). When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes (BST, LX, DH, and DL) away from sensitive analog areas (REFIN, FB, CSH, and CSL).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and anode of the low-side Schottky). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the backside opposite the MOSFETs to keep LX, GND, DH, and the DL gatedrive lines short and wide. The DL and DH gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 9. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close as is practical to the load. Table 5 lists the design differences between the MAX17000 and MAX17000A.
*
*
*
Table 5. MAX17000 vs. MAX17000A Design Differences
MAX17000 STDBY = Low turns off VTT and overrides the SKIP setting, forcing the SMPS to enter a low-quiescent current ultra-skip mode. MAX17000A STDBY = Low only turns off VTT rail, and does not affect SMPS operation.
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KELVIN SENSE VIAS UNDER THE INDUCTOR (SEE EVALUATION KIT) POWER STAGE LAYOUT (TOP SIDE OF PCB)
OUTPUT
INDUCTOR L1 CSL CSH RNTC R2 R1
COUT
COUT
POWER GROUND
CEQ
CIN1
KELVIN-SENSE VIAS TO INDUCTOR PAD INDUCTOR DCR SENSING INPUT
SMPS
CONNECT THE EXPOSED PAD TO ANALOG GROUND VTTI BYPASS CAPACITOR
CONNECT AGND AND PGND1 TO THE CONTROLLER AT THE EXPOSED PAD VDD BYPASS CAPACITOR
VIA TO POWER GROUND VCC BYPASS CAPACITOR VTT BYPASS CAPACITOR X-RAY VIEW. IC MOUNTED ON BOTTOM SIDE OF PCB.
IC LAYOUT
Figure 9. PCB Layout Example
Chip Information
TRANSISTOR COUNT: 7856 PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 24 TQFN PACKAGE CODE T2444-4 DOCUMENT NO. 21-0139
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Complete DDR2 and DDR3 Memory Power-Management Solution MAX17000A
Revision History
REVISION NUMBER 0 1 REVISION DATE 10/8 12/8 Initial release. Minor edits throughout. DESCRIPTION PAGES CHANGED -- 8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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